Battery removal and insertion scheme

Abstract

A device comprising a system-on-a-chip (SoC) is provided. The SoC is configured to receive information from a power management integrated circuit (PMIC) that a battery in the device was removed or will be removed, and store context data associated with the device based on the received information. The SoC further includes a battery event manager. The battery event manager is configured to store the context data associated with the device based on a timer. If the timer is greater than a first timer threshold, the battery event manager transitions the boot core to a deeper low-power mode (LPM) than a current LPM and the SoC to a sleep state. If the timer is greater than a second timer threshold, the battery event manager wakes up dynamic random access memory (DRAM) and copies the context data from the DRAM into non-volatile memory.

Dependencies are inferred from the claim text.