Voltage drop control circuit for a low power ldo regulator

A device comprising a voltage regulator having an input coupled to receive a supply voltage and an output configured to provide a regulated voltage to a digital circuit, the voltage regulator comprising:

• an amplifier having a first input coupled to receive a reference voltage and a second input coupled to the output;
• a transistor having a first conduction terminal coupled to the supply voltage, a second conduction terminal coupled to the output, and a control terminal coupled to an output of the amplifier;
• a capacitor coupled between the supply voltage and a first node;
• a first switch coupled between the first node and a bias current source;
• a second switch coupled between the first node and the control terminal of the transistor;
• a non-overlapped phase generator configured to generate non-overlapping first and second control signals to control the first and second switches respectively, wherein:
• during an integration phase controlled by the first control signal, the first switch is closed to charge the capacitor with a voltage above the conduction terminal to control terminal voltage of the transistor, and
• during a sharing phase controlled by the second control signal, the second switch is closed to couple the charged capacitor to the control terminal of the transistor to adjust its control terminal voltage* for increasing current sourcing capability during high-frequency operation of the digital circuit;
• and
• a clock gating circuit configured to enable the non-overlapped phase generator.