Concurrent testing device and method for integrated circuit

A concurrent testing device for an integrated circuit, comprising a test processor (TP) (4), a Parameter Pattern compiler (PPC), a parameter test controller (PTC), and an instruments control bus (ICB), wherein

• the TP (4) comprises a timing generator (TG) (1), a pattern generator (2), a signal processor unit command generator (3), a pattern memory, a memory control, and an instruments control message generator (ICMG) (5);
• the memory control is respectively connected to the TG (1), the pattern generator (2), the signal processor unit command generator (3), and the ICMG (5), and the pattern generator (2) is respectively connected to the TG (1) and the signal processor unit command generator (3);
• the TG (1), the pattern generator (2), and the signal processor unit command generator (3) access the pattern memory through the memory control to obtain commands and data;
• the TG (1) is responsible for generating corresponding cycle and clock edge information of a current cycle;
• the pattern generator (2) is responsible for executing command requirements in a pattern file to achieve jump and loop, and controlling an access of the memory control to an address of the pattern memory;
• the signal processor unit command generator (3) generates a command signal for synchronously controlling digital test channel subsystems under the control of the pattern generator (2), achieving synchronous control on the subsystems;
• a pattern generator file processed by the TP (4) comprises two or more instrument control opcode combination vectors;
• each instrument control opcode combination vector is composed of a pattern generator command (11), a timing set (12), a digital channel list (13), and an analog device pin list (15);
• the pattern generator command (11) is used for generating a control timing required for pattern testing;
• the timing set (12) is used for defining precise timing information required for the pattern generator to generate each cycle;
• the digital channel list (13) is used for describing working states of various digital channels under different timing conditions in each cycle;
• the analog device pin list (15) is composed of instrument control opcodes;
• the PPC converts the instrument control opcodes into instruments control messages (ICM) according to a conversion table for instrument control opcodes and ICMs;
• and
• the PPC is connected to the PTC through the ICB.