Semiconductor package including integrated voltage regulator and capacitor

A semiconductor package comprising:

• a package substrate;
• an interposer arranged on the package substrate and including an integrated voltage regulator (IVR) chip and a first capacitor inside the interposer;
• a logic chip on the interposer;
• and
• a memory chip adjacent to the logic chip and mounted on the interposer,
• wherein the interposer comprises:
• a core layer having a first surface and a second surface opposite to the first surface;
• a first wiring layer formed on the first surface of the core layer;
• a second wiring layer formed on the second surface of the core layer;
• and
• a through-hole conductor electrically connected to the first wiring layer and the second wiring layer, and configured to penetrate the core layer from the first surface to the second surface, and
• wherein at least a portion of each of the IVR chip and the first capacitor overlap with each other in a vertical direction that is perpendicular to an upper surface of the package substrate.

A semiconductor package comprising:

• a package substrate including an inductor therein;
• an interposer arranged on the package substrate, and including an integrated voltage regulator (IVR) chip and a first capacitor inside the interposer;
• a logic chip on the interposer;
• and
• a memory chip adjacent to the logic chip and mounted on the interposer,
• wherein the interposer comprises:
• a core layer having a first surface and a second surface opposite to the first surface;
• a first wiring layer formed on the first surface of the core layer;
• a second wiring layer formed on the second surface of the core layer;
• and
• a through-hole conductor electrically connected to the first wiring layer and the second wiring layer, and configured to penetrate the core layer from the first surface to the second surface,
• wherein the IVR chip and the first capacitor are arranged inside the interposer between the first wiring layer and the second wiring layer, and
• wherein at least a portion of each of the inductor, the IVR chip, the first capacitor, and the logic chip overlap with each other in a vertical direction that is perpendicular to an upper surface of the package substrate.