Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorSeungmin KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor package is provided. The semiconductor package includes: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the package substrate; an adhesive film provided on an upper surface the first semiconductor chip and an upper surface of the second semiconductor chip; and a third semiconductor chip attached to the first semiconductor chip, the second semiconductor chip by the adhesive film. The first and second semiconductor chips have different heights, and a thickness of the adhesive film at a portion thereof contacting the first semiconductor chip is different from a thickness of the adhesive film at a portion thereof contacting the second semiconductor chip.
Claims20
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip mounted on the package substrate;
- a plurality of second semiconductor chips mounted on the package substrate, wherein the first semiconductor chip is arranged between the plurality of second semiconductor chips;
- an adhesive film provided on an upper surface of the first semiconductor chip and upper surfaces of the plurality of second semiconductor chips;
- and
- a third semiconductor chip attached to the first semiconductor chip and the plurality of second semiconductor chips by the adhesive film,
- wherein a distance from the package substrate to a bottom surface of the third semiconductor chip is greater at a central portion of the third semiconductor chip than at a periphery portion thereof, and
- wherein a portion of the adhesive film, that faces the upper surface of the first semiconductor chip, is concave.
A semiconductor package comprising:
- a printed circuit board;
- a first semiconductor chip mounted on the printed circuit board by a first ball grid array;
- a plurality of second semiconductor chips mounted on the printed circuit board by a second ball grid array, wherein the first semiconductor chip is arranged between the plurality of second semiconductor chips;
- an adhesive film provided on an upper surface of the first semiconductor chip and upper surfaces of the plurality of second semiconductor chips;
- and
- a third semiconductor chip attached to the first semiconductor chip and the plurality of second semiconductor chips by the adhesive film,
- wherein a distance from the printed circuit board to a portion of the third semiconductor chip positioned above the first semiconductor chip is less than a distance from the printed circuit board to a portion of the third semiconductor chip positioned above the plurality of second semiconductor chips, and
- wherein a portion of the adhesive film, that faces the upper surface of the first semiconductor chip, is convex.
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip mounted on the package substrate;
- a first bonding wire connecting the first semiconductor chip to the package substrate;
- a plurality of second semiconductor chips mounted on the package substrate around the first semiconductor chip;
- a plurality of second bonding wires connecting the plurality of second semiconductor chips to the package substrate;
- an adhesive film provided on an upper surface of the first semiconductor chip and upper surfaces of the plurality of second semiconductor chips;
- and
- a third semiconductor chip attached to the first semiconductor chip and the plurality of second semiconductor chips by the adhesive film,
- wherein each of the plurality of second semiconductor chips comprises a plurality of stacked volatile memories,
- wherein the third semiconductor chip comprises a plurality of stacked non-volatile memories,
- wherein a distance from the package substrate to a portion of the third semiconductor chip positioned above the first semiconductor chip is greater than a distance from the package substrate to a portion of the third semiconductor chip positioned above the plurality of second semiconductor chips, and
- wherein a sidewall of one of the plurality of second semiconductor chips is provided on a same plane as a sidewall of the third semiconductor chip.
Dependencies are inferred from the claim text.