Method for Increasing Pin Alignment Accuracy for a Power Semiconductor Module
AssigneeInfineon Technologies AG
InventorMarco Ludwig
Life of this patent
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Abstract
A method for increasing overall pin alignment accuracy for a power semiconductor module having a plurality of pins includes attaching the plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly; aligning a distal end of each of the pins with an alignment feature of an electrically insulative housing using a jig; and after the aligning, attaching the housing to the power semiconductor subassembly. The housing is attached to the subassembly such that the housing and the substrate together define an interior space in which the pins and the one or more power semiconductor dies are disposed. The pins jut out beyond the housing.
Claims20
A method for increasing overall pin alignment accuracy for a power semiconductor module having a plurality of pins, the method comprising:
- attaching the plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly;
- aligning a distal end of each of the pins with an alignment feature of an electrically insulative housing using a jig;
- and
- after the aligning, attaching the housing to the power semiconductor subassembly such that the housing and the substrate together define an interior space in which the pins and the one or more power semiconductor dies are disposed,
- wherein the pins jut out beyond the housing.
A method for forming a power semiconductor module having a plurality of pins, the method comprising:
- attaching the plurality of pins and one or more power semiconductor dies to a first side of a substrate to form a power semiconductor subassembly;
- aligning a distal end of each of the pins with an alignment feature of an electrically insulative housing using a jig;
- and
- after the aligning, attaching the housing to the power semiconductor subassembly such that the housing and the substrate together define an interior space in which the pins and the one or more power semiconductor dies are disposed,
- wherein the pins jut out beyond the housing,
- wherein the aligning comprises:
- placing the housing on the jig such that the alignment feature of the housing mates with a first alignment feature of the jig;
- and
- placing the power semiconductor subassembly on the housing such that the distal end of each of a subset of the pins mates with a second alignment feature of the jig.
Dependencies are inferred from the claim text.