Integrated circuit structures having memory with backside power delivery
AssigneeIntel Corporation
InventorsAbhishek Anil SHARMA, Wilfred GOMES
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Abstract
Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.
Claims20
An integrated circuit structure, comprising:
- a front side structure comprising:
- a device layer;
- and
- a plurality of metallization layers above the device layer, the plurality of metallization layers comprising 10 or more metal layers, the 10 or more metal layers comprising signal lines;
- and
- a backside power delivery structure coupled to the frontside structure, the backside power delivery structure comprising:
- a first backside metal layer below and conductively coupled to the device layer;
- a via below and coupled to the first backside metal layer;
- a second backside metal layer below and coupled to the via;
- and
- a conductive bump coupled to the second backside metal layer.
An integrated circuit structure, comprising:
- a device layer;
- a first plurality of metallization layers above and conductively coupled to the device layer, the first plurality of metallization layers comprising 12 or more metal layers, the 12 or more metal layers comprising signal lines;
- a second plurality of metallization layers below and conductively coupled to the device layer on a side of the device layer opposite the first plurality of metallization layers, the second plurality of metallization layers comprising two or more metal layers, the two or more metal layers comprising power structures;
- and
- a conductive bump conductively coupled to a metallization layer of the second plurality of metallization layers.
A method of fabricating an integrated circuit structure, the method comprising:
- forming a front side structure comprising a device layer, and a plurality of metallization layers above the device layer, the plurality of metallization layers comprising 10 or more metal layers, the 10 or more metal layers comprising signal lines;
- and
- forming a backside power delivery structure coupled to the frontside structure, the backside power delivery structure comprising a first backside metal layer below and conductively coupled to the device layer, a via below and coupled to the first backside metal layer, a second backside metal layer below and coupled to the via, and a conductive bump coupled to the second backside metal layer.
Dependencies are inferred from the claim text.