In-situ test structure at wafer scribe line for pad corrosion monitoring and testing

A corrosion test system, comprising:

• a wafer, comprising:
• a die region comprising one or more bond pads;
• a wafer scribe region arranged outside of the die region;
• and
• a voltage divider comprising:
• a first test pad;
• a second test pad;
• a third test pad;
• an unexposed trace coupled to the first test pad and the second test pad, wherein the unexposed trace is arranged inside the wafer, and wherein the unexposed trace is configured to conduct a current and induce a first voltage drop representative of a reference value;
• and
• an exposed trace coupled to the second test pad and the third test pad, wherein the exposed trace is arranged on the wafer, in the wafer scribe region, and wherein the exposed trace is configured to conduct the current and induce a second voltage drop representative of a test value,
• wherein a comparison value of the reference value and the test value is indicative of an amount of a chemically-induced corrosion at the one or more bond pads;
• a power supply configured to induce the current;
• a plurality of test probes configured to measure the reference value and the test value;
• and
• a processing circuit configured to calculate a measurement value based on the reference value and the test value, and detect a chemically-induced corrosion at the exposed trace based on the measurement value satisfying a threshold.

A method of performing a corrosion test on a die integrated in a wafer, the method comprising:

• inducing, by a power supply, a current to flow through test structures configured as a voltage divider, wherein the voltage divider comprises:
• a first test pad formed on the wafer;
• a second test pad formed on the wafer;
• a third test pad formed on the wafer;
• an unexposed trace formed inside the wafer, wherein the unexposed trace is coupled to the first test pad and the second test pad, and wherein the unexposed trace is configured to conduct a current and induce a first voltage drop representative of a reference value;
• and
• an exposed trace formed on the wafer, outside of the die, wherein the exposed trace is coupled to the second test pad and the third test pad, and wherein the exposed trace is configured to conduct the current and induce a second voltage drop representative of a test value,
• measuring, by a processing circuit, the reference value and the test value using a plurality of test probes applied to the first test pad, the second test pad, and the third test pad, respectively;
• calculating, by the processing circuit, a measurement value based on the reference value and the test value;
• and
• detecting, by the processing circuit, a corrosion at the exposed trace based on the measurement value satisfying a threshold, the corrosion at the exposed trace being indicative of a presence of a corrosion at one or more bond pads of the die.

A method of manufacturing a wafer assembly, the method comprising:

• forming the wafer assembly, including:
• forming one or more bond pads in a die region;
• and
• forming a plurality of test structures in a voltage divider configuration, the plurality of test structures including:
• a first test pad formed on the wafer assembly;
• a second test pad formed on the wafer assembly;
• a third test pad formed on the wafer assembly;
• an unexposed trace formed inside the wafer assembly, wherein the unexposed trace, corresponding to a first leg of the voltage divider configuration, is coupled to the first test pad and the second test pad;
• and
• an exposed trace formed on the wafer assembly, outside of the die region, wherein the exposed trace, corresponding to a second leg of the voltage divider configuration, is coupled to the second test pad and the third test pad, and
• wherein a comparison value of a resistance of the unexposed trace and a resistance of the exposed trace is associated with an amount of corrosion at the one or more bond pads.

A semiconductor die, comprising:

• a die region comprising one or more bond pads coupled to one or more integrated circuits located within the die region;
• a wafer scribe region arranged outside of the die region, the wafer scribe region defining outer edges of the semiconductor die;
• a test pad arranged on a die surface of the die region;
• and
• an unexposed trace coupled to the test pad by a conductive structure that extends from the test pad, into the semiconductor die, to the unexposed trace,
• wherein the unexposed trace is arranged inside the semiconductor die, and
• wherein the unexposed trace extends laterally from the conductive structure to an outer edge of the semiconductor die defined by the wafer scribe region.