Bulk inclusion prediction model for wafer cutting technology
AssigneeSTMicroelectronics International N.V.
InventorJimmy THORNBERG
Life of this patent
Estimating the term…
Abstract
A system and method reliably sort wafers as suitable or unsuitable for processing. A plurality of first test wafers are initially sliced from a semiconductor ingot. A first surface analysis process is performed on each of the first test wafers to generate first surface defect data. A plurality of second test wafers are formed from the first test wafers by bonding the first test wafers to respective substrates. A second surface analysis process is then performed on the second test wafers to generate second surface defect data. A wafer sorting model is generated from the first and second surface defect data. Subsequently, embodiments of the present disclosure utilize the model to sort wafers after performing the first surface analysis process on the wafers.
Claims20
A method, comprising:
- forming a plurality of first test wafers by slicing a first semiconductor ingot;
- generating first test surface defect data by performing a first surface analysis process on the first test wafers with a first surface analysis system;
- forming a plurality of second test wafers from the first test wafers;
- generating second test surface defect data by performing a second surface analysis process on the second test wafers with a second surface analysis system;
- and
- generating a surface defect analysis model based on the first test surface defect data and the second test surface defect data.
A method, comprising:
- forming a plurality of first wafers from a semiconductor ingot;
- generating surface defect data by performing a surface analysis process on the first wafers;
- sorting the first wafers into a first group and a second group by comparing the surface defect data to a surface defect threshold;
- generating, from the first wafers of the first group, a plurality of second wafers;
- and
- discarding the first wafers of the second group.
A system, comprising:
- one or more memories configured to store software instructions;
- one or more processors configured to execute the software instructions to perform a process including:
- receiving, for each of a plurality of first wafers, a surface defect count based on a first surface analysis process of the first wafers;
- comparing, for each first wafer, the surface defect count to a surface defect threshold;
- sorting each first wafer into a first group if the surface defect count is less than the surface defect threshold;
- and
- sorting each first wafer into a second group if the surface defect count is greater than the surface defect threshold.
Dependencies are inferred from the claim text.