Deep trench capacitors and methods of forming the same

A structure comprising:

• a semiconductor substrate;
• a first trench formed in the substrate, the first trench including a first trench bottom and a first trench plurality of sides;
• a first group of alternating electrode and dielectric layers formed in the first trench, the first group of alternating layers covering the first trench bottom and the first trench plurality of sides, and the first group of alternating layers including a first metallic electrode layer, a second metallic electrode layer and a first dielectric layer disposed between the first and second metallic electrode layers to form a first capacitor, each of the first and second metallic electrode layers including a first longitudinal end and a second longitudinal end;
• a filler dielectric region formed in the first trench in a center region of the trench, the filler dielectric region extending along a longitudinal length of the first trench and the filler dielectric region forming a core dielectric region of the first trench which is at least partially encased by the first group of alternating layers;
• and
• a thin film transistor (TFT) structure formed on the first longitudinal end of the first metallic electrode layer, the TFT structure including a gate region, a dielectric region and a semiconductor region operatively connected to the first metallic electrode layer, the TFT structure formed to control electrical conductivity from the TFT gate to the first metallic electrode layer by the application of a gate voltage to switch on and off a capacitance provided by the first capacitor.

A method comprising:

• forming a first deep trench capacitor structure in a first semiconductor substrate, the first deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the first substate, and the plurality of planarized metal contacts extending into an intermetal region formed on the first semiconductor substrate;
• forming a second deep trench capacitor structure in a second semiconductor substrate, the second deep trench capacitor structure including a plurality of planarized metal contacts electrically connected to a plurality of electrodes within a trench formed in the second substate, and the plurality of planarized metal contacts extending into an intermetal region formed on the second semiconductor substrate;
• bonding the first deep trench capacitor structure to the second deep trench capacitor structure by bonding each of the first deep trench capacitor structure plurality of planarized metal contacts to a respective each of the second deep trench capacitor structure plurality of planarized metal contacts, thereby electrically connecting the first deep trench capacitor structure and the second deep trench capacitor structure;
• and
• forming a first IC interconnection structure including a plurality of metal contacts electrically connected to the plurality of electrodes within the first deep trench capacitor structure to provide an integrated circuit (IC) including a stacked deep trench capacitor (DTC) structure.