Metal-semiconductor field-effect transistors for gallium arsenide technologies
AssigneeSkyworks Solutions, Inc.
InventorBrian James Johnson
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Abstract
Metal-semiconductor field-effect transistors (MESFETs) for gallium arsenide (GaAs) technologies are disclosed herein. In certain embodiments, a semiconductor wafer includes a substrate, a GaAs channel layer formed over the substrate, an etch stop layer formed over the GaAs channel layer, and a GaAs subcollector layer formed over the etch stop layer. The GaAs subcollector layer is patterned to form a source region and a drain region for a GaAs MESFET, as well as a recess between the source region and the drain region. Additionally, a metal gate of the MESFET is formed over the etch stop layer in the recess.
Claims20
A semiconductor wafer comprising:
- a substrate;
- a gallium arsenide channel layer formed over the substrate;
- an etch stop layer formed over the gallium arsenide channel layer;
- and
- a gallium arsenide subcollector layer formed over the etch stop layer, the gallium arsenide subcollector layer patterned to form a source region and a drain region for a metal-semiconductor field-effect transistor, and a recess between the source region and the drain region;
- and
- a metal gate of the metal-semiconductor field-effect transistor formed over the etch stop layer in the recess.
A method of semiconductor fabrication, the method comprising:
- forming a source contact and a drain contact on a gallium arsenide subcollector layer that is over an etch stop layer, the etch stop layer being over a gallium arsenide channel layer, and the gallium arsenide channel layer being over a substrate;
- patterning the gallium arsenide subcollector layer to form a source region and a drain region for a metal-semiconductor field-effect transistor and a recess between the source region and the drain region, the source contact being on the source region and the drain contact being on the drain region;
- and
- forming a metal gate of the metal-semiconductor field-effect transistor over the etch stop layer in the recess.
A gallium arsenide integrated circuit comprising:
- a substrate;
- and
- a metal-semiconductor field-effect transistor formed over the substrate, the metal-semiconductor field-effect transistor including a gallium arsenide channel structure over the substrate, an etch stop layer structure over the gallium arsenide channel structure, a source region formed over the etch stop layer structure from a first portion of a gallium arsenide subcollector layer, a drain region formed over the etch stop layer structure from a second portion of the gallium arsenide subcollector layer, and a metal gate formed over the etch stop layer in a recess between the source region and the drain region.
Dependencies are inferred from the claim text.