Method of forming a recessed gate terminal, and wafer including the recessed gate terminal and having reduced warpage

A wafer or die comprising:

• a solid body having a first side and a second side opposite to one another along a direction;
• a trench extending in the solid body from the first side towards the second side, ending within the solid body;
• a gate dielectric layer in the trench and covering with structural continuity lateral and bottom walls of the trench;
• a first gate conductive layer in the trench, on the gate dielectric layer, and extending with structural continuity along the lateral wall up to the first side;
• a filling layer in the trench and on the first gate conductive layer, the filling layer partially fills the trench from the bottom wall towards the first side;
• and
• a second gate conductive layer in the trench and on the filling layer.

A method, comprising:

• forming a trench in a first surface of a solid body, the trench having a lateral surface and a bottom surface;
• forming a gate dielectric layer on the first surface, the lateral surface, and the bottom surface;
• forming a first gate conductive layer on the gate dielectric layer, the first gate conductive layer being spaced from the first surface, the lateral surface, and the bottom surface by the gate dielectric layer;
• forming a filling layer on the first gate conductive layer, the filling layer being spaced from the lateral surface and the bottom surface by the first gate conductive layer and the gate dielectric layer, the filling layer filling a first portion of the trench;
• and
• forming a second gate conductive layer on the filling layer, the second gate conductive layer being spaced from the lateral surface by the first gate conductive layer and the gate dielectric layer, the second gate conductive layer being spaced from the bottom surface by the first gate conductive layer, the gate dielectric layer, and the filling layer, the second gate conductive layer filling a second portion of the trench.