US 2026/0247669 A1 · BURIED P+ EPITAXIAL LAYERS FOR ROBUST ISOLATION IN HIGH-VOLTAGE BIPOLAR-CMOS-DMOS DEVICES

Abstract

Techniques are described for robust transistor isolation in high-voltage Bipolar-CMOS-DMOS (HV-BCD) devices. Embodiments incorporate silicon-boron (Si:B) epitaxially grown (EPI) buried layers into HV-BCD devices, such between a P-substrate and a P-EPI layer. Such structures reduce parasitic NPN transistor effects by controlling the alpha ratio, linked to boron concentration and electron diffusion barriers. Some embodiments add co-doped layers with oxygen and/or carbon to control P-EPI layer features, such as thickness, dopant profile, and breakdown voltage (Vbd). Co-doping can be achieved by low-pressure chemical vapor deposition (LPCVD).

Claims20

Dependent claims

A method for producing electrical isolation between high-voltage bipolar-CMOS-DMOS (HV-BCD) devices, the method comprising:

growing a P+ silicon-boron (Si:B) epitaxial (EPI) layer on a P− substrate of a semiconductor device having a plurality of HV-BCD devices;
growing a P− EPI layer on the P+ Si:B EPI layer;
forming a P+ diffusion region extending from the P+ Si:B EPI layer;
and
forming a deep trench isolation (DTI) structure in a region between adjacent ones of the HV-BCD devices to penetrate at least the P− EPI layer and the P+ Si:B EPI layer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/057,877Filed 19 Feb 2025

Published

20 Aug 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 62/112
Constructional design considerations for preventing surface leakage or controlling electric field concentration: for preventing surface leakage…
H10D 62/371
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
H10D 62/01
Semiconductor bodies, or regions thereof, of devices having potential barriers: manufacture or treatment
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Buried p+ epitaxial layers for robust isolation in high-voltage bipolar-cmos-dmos devices

Life of this patent

Buried p+ epitaxial layers for robust isolation in high-voltage bipolar-cmos-dmos devices

Life of this patent

Abstract

Claims20