Vertical field effect transistor device and method of fabrication

A vertical gallium nitride (GaN) field effect transistor (FET) device comprising:

• an n-type GaN epitaxial layer overlying a GaN substrate;
• a recessed region formed between a first finger region and a second finger region, wherein the first and second finger regions each comprise a portion of the n-type GaN epitaxial layer, an n+ type portion, and a capping layer;
• a p-type gate region configured from a selective area implant region at a bottom portion of the recessed region;
• an n-type GaN channel;
• an n+ type source configured from the n+ type portion of the first and second finger regions;
• an extended drain region configured from a portion of n-type GaN region underlying the recessed region;
• an n+ type GaN region formed by epitaxial growth directly overlying a backside region of the GaN substrate;
• and
• a backside drain contact region configured from the n+ type GaN region overlying the backside region.