Orthogonal inner spacer

A semiconductor integrated circuit device comprising:

• a gate around a plurality of channels;
• a first orthogonal inner spacer below a bottommost channel of the plurality of channels, the first orthogonal inner spacer comprising a first vertical portion and a first horizontal base portion that extends inwardly beyond a plane that is coplanar with a first sidewall of the gate;
• and
• a second orthogonal inner spacer below the bottommost channel of the plurality of channels, the second orthogonal inner spacer comprising a second vertical portion and a second horizontal base portion that extends inwardly beyond a plane that is coplanar with a second sidewall of the gate.

A method of forming a semiconductor integrated circuit device comprising:

• forming a first sacrificial nanolayer directly upon a substrate;
• forming a second sacrificial nanolayer directly upon the first sacrificial nanolayer;
• forming an orthogonal inner spacer opening by indenting the first sacrificial nanolayer to a first horizontal depth and the second sacrificial nanolayer to a second horizontal depth greater than the first horizontal depth;
• and
• forming an orthogonal inner spacer within the orthogonal inner spacer opening.