US 2026/0247647 A1 · SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns; a second active pattern including a second lower pattern and second sheet patterns, a height of the second lower pattern being smaller than a height of the first lower pattern; a first gate structure on the first lower pattern; a second gate structure on the second lower pattern; a first source/drain pattern on the first lower pattern and connected to the first sheet patterns; and a second source/drain pattern on the second lower pattern and connected to the second sheet patterns, wherein a width of an upper surface of the first lower pattern is different from a width of an upper surface of the second lower pattern, and wherein a number of first sheet patterns is different from a number of second sheet patterns.

Claims21

Dependent claims

(canceled)

A method of manufacturing a semiconductor device, comprising:

sequentially forming a first sacrificial film and a first channel film on a second area of a substrate;
forming a lower buffer film on a first area of the substrate;
forming a stacked structure comprising a plurality of second sacrificial films and a plurality of second channel films alternately stacked on the first channel film and the lower buffer film;
forming a first upper pattern comprising a plurality of first sacrificial channel patterns and a plurality of first channel patterns alternately stacked on the lower buffer film by patterning the stacked structure on the first area of the substrate;
forming a second upper pattern comprising a plurality of second sacrificial channel patterns and a plurality of second channel patterns alternately stacked on the substrate by patterning the first sacrificial film, the first channel film, and the stacked structure on the second area of the substrate;
forming a first lower pattern under the first upper pattern by patterning a portion of the substrate and the lower buffer film;
forming a second lower pattern under the second upper pattern by patterning a portion of the substrate, wherein an upper surface of the second lower pattern is lower than an upper surface of the first lower pattern;
forming a first field insulating film exposing the first upper pattern on the first area of the substrate;
forming a second field insulating film exposing the second upper pattern on the second area of the substrate;
and
removing the plurality of first sacrificial channel patterns and the plurality of second sacrificial channel patterns.

8 more elements

A method of manufacturing a semiconductor device, comprising:

sequentially forming a first sacrificial film and a first channel film on a first area and a second area of a substrate;
removing the first sacrificial film on the first area of the substrate and the first channel film on the first area of the substrate;
forming a lower buffer film on the first area of the substrate;
forming a stacked structure comprising a plurality of second sacrificial films and a plurality of second channel films alternately stacked on the first channel film on the second area of the substrate and on the lower buffer film;
forming a first upper pattern comprising a plurality of first sacrificial channel patterns and a plurality of first channel patterns alternately stacked on the lower buffer film by patterning the stacked structure on the first area of the substrate;
forming a second upper pattern comprising a plurality of second sacrificial channel patterns and a plurality of second channel patterns alternately stacked on the substrate by patterning the first sacrificial film, the first channel film, and the stacked structure on the second area of the substrate;
forming a first lower pattern under the first upper pattern by patterning a portion of the substrate and the lower buffer film;
forming a second lower pattern under the second upper pattern by patterning a portion of the substrate, wherein an upper surface of the second lower pattern is lower than an upper surface of the first lower pattern;
forming a first field insulating film exposing the first upper pattern on the first area of the substrate;
forming a second field insulating film exposing the second upper pattern on the second area of the substrate, wherein an upper surface of the second field insulating film is lower than an upper surface of the first field insulating film;
and
removing the plurality of first sacrificial channel patterns and the plurality of second sacrificial channel patterns.

9 more elements

A method of manufacturing a semiconductor device, comprising:

sequentially forming a first sacrificial film and a first channel film on a first area and a second area of a substrate;
forming a mask pattern on the first channel film on the second area of the substrate;
removing the first sacrificial film and the first channel film exposed from the mask pattern;
forming a lower buffer film on the first area of the substrate;
exposing the first channel film on the second area of the substrate by removing the mask pattern;
forming a stacked structure comprising a plurality of second sacrificial films and a plurality of second channel films alternately stacked on the first channel film and the lower buffer film;
forming a first upper pattern comprising a plurality of first sacrificial channel patterns and a plurality of first channel patterns alternately stacked on the lower buffer film by patterning the stacked structure on the first area of the substrate;
forming a second upper pattern comprising a plurality of second sacrificial channel patterns and a plurality of second channel patterns alternately stacked on the substrate by patterning the first sacrificial film, the first channel film, and the stacked structure on the second area of the substrate;
forming a first lower pattern under the first upper pattern by patterning a portion of the substrate and the lower buffer film;
forming a second lower pattern under the second upper pattern by patterning a portion of the substrate, wherein an upper surface of the second lower pattern is lower than an upper surface of the first lower pattern;
forming a pre-field insulating film covering an upper surface of the first upper pattern and an upper surface of the second upper pattern on the substrate;
forming a first field mask pattern on the pre-field insulating film on the second area of the substrate;
forming a first field insulating film exposing the first upper pattern by removing a portion of the pre-field insulating film exposed from the first field mask pattern;
exposing the pre-field insulating film on the second area of the substrate by removing the first field mask pattern;
forming a second field mask pattern covering the first upper pattern on the first field insulating film;
forming a second field insulating film exposing the second upper pattern by removing a portion of the pre-field insulating film exposed from the second field mask pattern, wherein an upper surface of the second field insulating film is lower than an upper surface of the first field insulating film;
exposing the first upper pattern by removing the second field mask pattern;
and
removing the plurality of first sacrificial channel patterns and the plurality of second sacrificial channel patterns.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/647,627Filed 14 Apr 2026

Priority

KR 10-2022-013634121 Oct 2022

Published

20 Aug 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…
H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims21