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US 2026/0246468 A1Published application
Physically unclonable cell with single transistor types to improve voltage and temperature stability
AssigneeNVIDIA Corporation
InventorsMahmut Ersin Sinangil, Sudhir Shrikantha Kudva, Nikola Nedovic, John Poulton, Carl Thomas Gray
Life of this patent
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Abstract
Physically unclonable function cells based on bit-storing machine-memory circuits include a pair of parallel circuit branches, each of the parallel branches including a first transistor configured to be always-ON when the physically unclonable function cell is powered, and a second transistor cross-coupled to an opposite one of the parallel branches.
Claims25
A machine-memory cell comprising:
- a pair of parallel branches;
- each of the branches consisting of:
- a first transistor configured to be always-ON when the memory cell is powered;
- and
- a second transistor cross-coupled to an opposite one of the branches.
2 more elements
A physically unclonable function (PUF) cell comprising:
- a pair of parallel branches coupled between a power node and a ground node, each branch consisting of:
- a first transistor configured to be always-ON when the PUF cell is enabled;
- a second transistor cross-coupled to an opposite one of the branches;
- a header device or a footer device configured to selectively enable current flow through the PUF cell;
- and
- a pair of feedback paths each coupled from an output of a respective one of the parallel branches to each first transistor of the PUF cell, wherein the feedback paths are configured to be enabled by a delayed version of an enable signal controlling the header device or footer device.
3 more elements
A system comprising a bank of physically unclonable function (PUF) cells, comprising:
- a plurality of physically unclonable function cells, each PUF cell comprising:
- a pair of parallel branches coupled between a power node and a ground node, each branch consisting of:
- a first transistor configured to be always-ON when the PUF cell is enabled;
- and
- a second transistor cross-coupled to an opposite one of the branches;
- a plurality of header devices and/or footer devices configured to control activation of the PUF cells;
- and
- control logic configured to sequentially enable subsets of the PUF cells via the header devices and/or footer devices such that activation of the PUF cells is temporally staggered.
5 more elements
Dependencies are inferred from the claim text.