Method for Designing an Integrated Circuit

A method of fabricating an integrated circuit comprising:

• designing the integrated circuit according to the method comprising:
• obtaining a functional description of the integrated circuit;
• and
• generating, based on the functional description, a layout of the integrated circuit, wherein the layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout, wherein the first cell row has a first row boundary, the second cell row has a second row boundary, and the first and second cell rows are separated by a shared third row boundary,
• wherein generating the layout comprises placing a first and a second cell of a standard cell library in the layout, each cell having a cell height equal to the row height, and comprising:
• first and second cell edges extending in parallel in the horizontal direction,
• at least one CFET device having an active pattern extending in the horizontal direction, and
• at least one local interconnect disposed on the second cell edge and configured to connect to a top and/or bottom source/drain, S/D, of a CFET device of the at least one CFET device of the cell,
• wherein the first and second cells are placed in the first and second cell rows, respectively, such that:
• the first cell edge of the first cell aligns with the first row boundary,
• the first cell edge of the second cell aligns with the second row boundary, and
• the second cell edges of the first and second cells align with and abut each other along the third row boundary,
• wherein the at least one local interconnect of the first and second cells align to form a common row of local interconnects on the third row boundary, and
• wherein the placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap
• wherein the method obtains a layout of the integrated circuit;
• and
• fabricating the integrated circuit in accordance with the layout.

A system for designing an integrated circuit comprising complementary field-effect transistors, CFETs, the system comprising:

• a processing device;
• and
• a computer-readable storage medium storing instructions configured to, when executed by the processing device, cause the processing device to perform a method comprising:
• obtaining a functional description of the integrated circuit;
• and
• generating, based on the functional description, a layout of the integrated circuit, wherein the layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout, wherein the first cell row has a first row boundary, the second cell row has a second row boundary, and the first and second cell rows are separated by a shared third row boundary,
• wherein generating the layout comprises placing a first and a second cell of a standard cell library in the layout, each cell having a cell height equal to the row height, and comprising:
• first and second cell edges extending in parallel in the horizontal direction,
• at least one CFET device having an active pattern extending in the horizontal direction, and
• at least one local interconnect disposed on the second cell edge and configured to connect to a top and/or bottom source/drain, S/D, of a CFET device of the at least one CFET device of the cell,
• wherein the first and second cells are placed in the first and second cell rows, respectively, such that:
• the first cell edge of the first cell aligns with the first row boundary,
• the first cell edge of the second cell aligns with the second row boundary, and
• the second cell edges of the first and second cells align with and abut each other along the third row boundary,
• wherein the at least one local interconnect of the first and second cells align to form a common row of local interconnects on the third row boundary, and
• wherein the placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.