US 2026/0246455 A1Published application

Circuitry for phase alignment of multiple frequency dividers

AssigneeRealtek Semiconductor Corp.

InventorsChi-Ling Hung, Kuo-Wei Wu

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Abstract

The present invention provides a circuitry including a clock buffer, a first circuit module, and a second circuit module. The clock buffer is configured to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider configured to divide the first clock signal to generate a plurality of first divided clock signals. The second circuit module includes a second frequency divider configured to divide the first clock signal to generate a plurality of second divided clock signals. During the frequency division operation, both the first circuit module and the second circuit module utilize the second clock signal for phase alignment, thereby ensuring that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.

Claims10

Dependent claims

A circuitry, comprising:

a clock buffer, configured to generate a first clock signal and a second clock signal;
a first circuit module, comprising a first frequency divider, wherein the first frequency divider is configured to receive the first clock signal and the second clock signal, and perform a frequency division operation on the first clock signal to generate a plurality of first divided clock signals;
and
a second circuit module, comprising a second frequency divider, wherein the second frequency divider is configured to receive the first clock signal and the second clock signal, and perform the frequency division operation on the first clock signal to generate a plurality of second divided clock signals;
wherein the first circuit module and the second circuit module utilize the second clock signal to perform a phase alignment operation during the frequency division operation, so that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/534,773Filed 10 Feb 2026
Priority: TW 11510107012 Jan 2026
Published: 20 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 5/05
By increasing duration; by decreasing duration: by the use of clock signals or other time reference signals
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…
H03K 5/15006
Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors: with two programmable outputs
H03K
Pulse technique