Current monitoring scheme for low-side body current sensing of vertical power field effect transistor

A current monitoring circuit coupled to sense a current in a power field effect transistor (FET) configured as a low-side power FET in a power stage, a drain terminal of the low-side power FET being a switching output node, the current monitoring circuit comprising:

• a sense field effect transistor (FET) having a drain terminal connected to the drain terminal of the low-side power FET, a gate terminal connected to a gate terminal of the low-side power FET, and a source terminal being a sense node, the sense FET conducting a current indicative of the current flowing through the low-side power FET including a channel current flowing through a channel region of the low-side power FET and a body diode current flowing through a body diode of the low-side power FET;
• a current sense circuit coupled to the sense node to bias the sense node to a first voltage being a voltage at the source terminal of the low-side power FET, the current sense circuit sensing a first sense current flowing in the sense FET;
• and
• a gain circuit coupled to the current sense circuit to selectively adjust a gain level of the first sense current,
• wherein the first sense current has a first gain level in response to sensing the channel current of the low-side power FET and the first sense current has a second gain level in response to sensing the body diode current of the low-side power FET;
• and wherein the gain circuit adjusts the first or second gain level of the first sense current to scale the first and second gain levels to a same gain level to provide a current output signal indicative of the channel current or the body diode current flowing through the low-side power FET;
• and
• wherein the gain circuit is engaged to reduce the gain level of the first sense current and the gain circuit is disengaged to leave the gain level of the first sense current unmodified.