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US 2026/0245645 A1Published application
Multi-level cell data encoding
OwnerWin-San KHWA, Jui-Jen WU +2inventors
InventorsWin-San KHWA, Jui-Jen WU, Jen-Chieh LIU, Meng-Fan CHANG
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Abstract
A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.
Claims20
1. A convolutional neural network system, comprising:
- a memory cell array including multi-level cells configured to store convolutional neural network weights;
- and
- an input data scramble circuit configured to store matched bit sets in one memory cell of the multi-level cells including the most significant bit of the convolutional neural network weight and the least significant bit of the convolutional neural network weight, such that if the one memory cell is inadvertently changed the impact on the inferences is between the larger impact of the most significant bit and the smaller impact of the least significant bit, and the input data scramble circuit is configured to store the matched bit sets in other memory cells of the multi-level cells including the most significant bit minus n of the convolutional neural network weight and the least significant bit plus n of the convolutional neural network weight, where n is a non-negative integer, such that if one of the other multi-level cells is inadvertently changed the impact on the inferences is between the larger impact of the higher order bit and the smaller impact of the lower order bit.
A convolutional neural network system, comprising:
- a memory cell array including multi-level cells configured to store convolutional neural network weights;
- and
- an input data scramble circuit configured to receive input data and store pairs of bits in each of the multi-level cells, the input data scramble circuit configured to store at least one pair of bits in one memory cell of the multi-level cells including the most significant bit of the convolutional neural network weight and the least significant bit of the convolutional neural network weight, such that if the one memory cell is inadvertently changed the impact on the inferences is between the larger impact of the most significant bit and the smaller impact of the least significant bit, and the input data scramble circuit is configured to store other pairs of bits in other memory cells of the multi-level cells including the most significant bit minus n of the convolutional neural network weight and the least significant bit plus n of the convolutional neural network weight, where n is a non-negative integer, such that if one of the other multi-level cells is inadvertently changed the impact on the inferences is between the larger impact of the higher order bit and the smaller impact of the lower order bit.
A method, comprising:
- obtaining input data that includes convolutional neural network weights;
- matching a most significant bit of a convolutional neural network weight and a least significant bit of the convolutional neural network weight in a matched bit set to be stored in one memory cell, such that if the one memory cell is inadvertently changed the impact on the inferences is between the larger impact of the most significant bit and the smaller impact of the least significant bit;
- matching a most significant bit minus n of the convolutional neural network weight and a least significant bit plus n of the convolutional neural network weight, where n is a positive integer, in other matched bit sets to be stored in other memory cells, such that if one of the other memory cells is inadvertently changed the impact on the inferences is between the larger impact of the higher order bit and the smaller impact of the lower order bit;
- and
- outputting the matched bit set and the other matched bit sets to a write driver;
- and
- writing the matched bit set and the other matched bit sets into multi-level cells of a memory cell array.
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Dependencies are inferred from the claim text.