Zq calibration circuit and memory device including the same

A memory device comprising:

• a memory cell array;
• a first pad and a second pad configured to input and output a first signal and a second signal, respectively, the first signal and the second signal being used to operate the memory cell array;
• and
• a ZQ calibration circuit configured to perform a ZQ calibration operation on the first pad and the second pad,
• wherein the ZQ calibration circuit includes:
• a first ZQ driver connected between a first voltage and a first node, an impedance of the first ZQ driver being adjusted based on a first calibration code;
• a first ZQ calibrator connected to the first node, the first ZQ calibrator configured to receive a first reference voltage and generate the first calibration code by performing a first calibration operation based on a voltage at the first node and the first reference voltage;
• a second ZQ driver connected between the first node and a ZQ pad, an impedance of the second ZQ driver being adjusted based on a second calibration code;
• and
• a second ZQ calibrator connected to the ZQ pad, the second ZQ calibrator configured to receive a second reference voltage different from the first reference voltage and generate the second calibration code by performing a second calibration operation based on a voltage at the ZQ pad and the second reference voltage, and
• wherein the first calibration operation and the second calibration operation are simultaneously performed.

A ZQ calibration circuit comprising:

• a first ZQ driver configured to operate based on a first power supply voltage, an impedance of the first ZQ driver being adjusted based on a first calibration code, the first ZQ driver including a plurality of first transistors connected in parallel between the first power supply voltage and a first node;
• a first ZQ calibrator connected to the first node, the first ZQ calibrator configured to receive a first reference voltage and generate the first calibration code by performing a first calibration operation based on a voltage at the first node and the first reference voltage;
• a second ZQ driver configured to operate based on a second power supply voltage having a voltage level lower than a voltage level of the first power supply voltage and equal to a voltage level of the first reference voltage, an impedance of the second ZQ driver being adjusted based on a second calibration code, the second ZQ driver including a plurality of second transistors connected in parallel between the first node and a ZQ pad;
• and
• a second ZQ calibrator connected to the ZQ pad, the second ZQ calibrator configured to receive a second reference voltage different from the first reference voltage and generate the second calibration code by performing a second calibration operation based on a voltage at the ZQ pad and the second reference voltage,
• wherein, when the first calibration operation is performed, the impedance of the first ZQ driver is adjusted by controlling on and off states of each of the plurality of first transistors such that a voltage level at the first node and the voltage level of the first reference voltage are equal to each other,
• wherein, when the second calibration operation is performed, the impedance of the second ZQ driver is adjusted by controlling on and off states of each of the plurality of second transistors such that a voltage level at the ZQ pad and a voltage level of the second reference voltage are equal to each other, and
• wherein the first calibration operation and the second calibration operation are simultaneously performed during a single ZQ interval in response to a single ZQ command.