Memory device and manufacturing method thereof

A memory device, comprising:

• a plurality of sub-cell regions respectively comprising a plurality of memory cells and arranged in a first direction;
• a plurality of contact regions between the plurality of sub-cell regions;
• a plurality of sub-wordlines extending in the first direction from the plurality of sub-cell regions to adjacent contact regions, wherein the plurality of sub-wordlines are spaced apart along a second direction intersecting the first direction;
• and
• a plurality of wordline interconnection lines that overlap at least some of the plurality of sub-cell regions, wherein the plurality of wordline interconnection lines extend in the first direction from the at least some of the plurality of sub-cell regions to the adjacent contact regions and overlap sub-wordlines adjacent to overlapping sub-wordlines in the first direction, in the adjacent contact regions,
• wherein at least some of the plurality of wordline interconnection lines are connected to the overlapping sub-wordlines in the adjacent contact regions, and the plurality of wordline interconnection lines are connected to sub-wordline drivers that overlap at least some of the plurality of sub-cell regions.

A manufacturing method of a memory device, comprising:

• forming a cell structure layer comprising a memory cell structure having sub-wordlines extending in a first direction in a plurality of sub-cell regions defined on a first substrate, wherein the sub-wordlines are spaced apart in a second direction, intersecting the first direction;
• inverting the cell structure layer and grinding the first substrate;
• forming a cell interconnection layer comprising wordline interconnection lines alternately overlapping sub-wordlines in the first direction and the second direction in the plurality of sub-cell regions, the wordline interconnection lines extending to adjacent contact regions to overlap adjacent sub-wordlines, on an upper surface of the cell structure layer;
• forming a circuit element layer by forming sub-wordline drivers in a plurality of unit areas defined on a second substrate;
• forming a circuit interconnection layer on an upper surface of the circuit element layer;
• and
• bonding the cell interconnection layer and the circuit interconnection layer so that the plurality of sub-cell regions and the plurality of unit areas overlap each other.