Read-only memory array for reducing the layout areas of capacitors and read-only memory thereof

A read-only memory array comprising:

• a plurality of common-source lines, arranged in parallel, comprising a first common-source line;
• a plurality of word lines arranged in parallel, wherein the plurality of word lines perpendicular to the plurality of common-source lines comprise a first word line;
• a plurality of bit lines arranged in parallel, wherein the plurality of bit lines perpendicular to the plurality of word line comprises a first bit line;
• and
• a plurality of read-only memories each coupled to one of the plurality of common-source lines, one of the plurality of word lines, and one of the plurality of bit lines, wherein each of the plurality of read-only memories comprises:
• an N-channel field-effect transistor (FET) with a source thereof coupled to the first common-source line;
• an electronic switch coupled between a drain of the N-channel FET and the first bit line;
• and
• a capacitor with one terminal thereof coupled to a gate of the N-channel FET and another terminal of the capacitor is coupled to the first word line, wherein the N-channel FET and the capacitor are formed in a P-type semiconductor region;
• wherein the capacitor comprises:
• a first N-type heavily-doped area formed in the P-type semiconductor region and coupled to the first word line;
• a first dielectric block;
• and
• an electrode block formed on the P-type semiconductor region through the first dielectric block and coupled to the gate of the N-channel FET, wherein the electrode block has a strip portion and finger portions vertical to the first strip portion, one end of each of the finger portions is connected to the strip portion, and another end of each of the finger portions extends to the first N-type heavily-doped area.