Verification response method for consumable chip and verification method for consumable container

A verification response method for a consumable chip, comprising:

• receiving, by a consumable chip, a verification instruction;
• wherein
• determining a verification time period of a verification response signal according to the verification instruction, and determining a verification level of each verification time period, wherein
• the verification time period comprises two groups of verification time periods, a first group of verification time periods is located in a first response cycle, a second group of verification time periods is located in a second response cycle, an initial verification level in the first group of verification time periods is a low-level signal, an initial verification level in a first verification time period of the second group of verification time periods is a high-level signal, and an initial verification level in a second verification time period of the second group of verification time periods is a low-level signal;
• and
• the verification response method comprises:
• outputting the high-level signal in half a clock cycle before the first group of verification time periods, outputting the low-level signal or a high-impedance state in the first group of verification time periods, outputting the high-level signal in the first verification time period of the second group of verification time periods, and outputting the low-level signal or the high-impedance state in the second verification time period of the second group of verification time periods.

A verification response method for a consumable chip, comprising:

• receiving, by a consumable chip, a verification instruction;
• wherein
• determining a verification time period of a verification response signal according to the verification instruction, and determining a verification level of each verification time period, wherein
• the verification time period comprises two groups of verification time periods, a first group of verification time periods is located in a first response cycle, a second group of verification time periods is located in a second response cycle, an initial verification level in the first group of verification time periods is a low-level signal, an initial verification level in a first verification time period of the second group of verification time periods is a high-level signal, and an initial verification level in a second verification time period of the second group of verification time periods is a low-level signal;
• and
• the verification response method comprises:
• after a first clock cycle of the second response cycle, outputting the high-level signal to a data signal line before the first verification time period of the second group of verification time periods arrives, and enabling a voltage of the data signal line to be maintained, in the first verification time period of the second group of verification time periods, above a threshold voltage determined as a high level.