Memory access instruction reordering
AssigneeArm Limited
InventorsRichard Roy GRISENTHWAITE, Thomas Philip SPEIER, Jade Ella Carla ALGLAVE
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AssigneeArm Limited
InventorsRichard Roy GRISENTHWAITE, Thomas Philip SPEIER, Jade Ella Carla ALGLAVE
Estimating the term…
An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry. The processing circuitry imposes an ordering requirement on one or more memory access instructions to prevent said one or more memory access instructions being reordered with respect to an ordering instruction. In response to an ordering limit hint instruction associated with a given ordering instruction, the processing circuitry relaxes the ordering requirement for a memory access instruction for which the ordering limit hint instruction appears in program order between the memory access instruction and the given ordering instruction.
An apparatus, comprising:
A method, comprising:
A non-transitory computer-readable medium storing a computer program comprising instructions which, when executed by a host data processing apparatus, control the host data processing apparatus to provide an instruction execution environment for execution of target program code, the computer program comprising:
Dependencies are inferred from the claim text.