Flexible architecture for floating-point and integer compute-in-memory

A method, comprising:

• selecting, by a processing system, a mode including at least one of a floating-point mode or an integer mode;
• selecting, by the processing system, a precision from multiple precisions;
• gating, by the processing system, portions of a compute engine responsive to the selection;
• producing, in the floating-point mode and by compute circuitry of the compute engine, a mantissa product and a product exponent and combining signs;
• aligning, in the floating-point mode and by alignment circuitry comprising a power-of-two generator and a selection network coupled to the compute circuitry, the mantissa product as part of multiplication using a power-of-two value corresponding to the product exponent;
• driving, in the integer mode and by the alignment circuitry, the selection network to perform integer multiplications of operand values;
• managing negative values using sign-handling circuitry, including performing two's-complement handling in the integer mode prior to accumulation;
• accumulating aligned products using accumulation circuitry comprising a plurality of parallel adder trees and a hierarchical output accumulator;
• and
• normalizing an output sum using normalization circuitry to form an output value in a numeric format.

An apparatus, comprising:

• operand registers for operand values;
• compute circuitry configured to produce a mantissa product and a product exponent;
• alignment circuitry comprising a power-of-two generator and a selection network coupled to the compute circuitry, the alignment circuitry being configured to:
• in a floating-point mode, align the mantissa product as part of multiplication using a power-of-two value corresponding to the product exponent;
• and
• in an integer mode, drive the selection network to perform integer multiplications of operand values;
• sign-handling circuitry configured to manage negative values, including two's-complement handling in the integer mode prior to accumulation;
• accumulation circuitry comprising a plurality of parallel adder trees and a hierarchical output accumulator;
• and
• normalization circuitry configured to form an output value in a numeric format.