Compute in memory architecture that allows flexible floating-point operations

A method of operating a compute engine of a computing system, comprising:

• selecting, by a processing system, a mode including at least a floating-point mode;
• performing format preprocessing, by format preprocessing circuitry arranged along input paths and coupled between an operand storage and at least one of a compute circuitry and an accumulation circuitry, configured to route element representations of different bit widths through shared lanes;
• in the floating-point mode, causing compute circuitry of the compute engine to produce a mantissa product and a product exponent;
• aligning, by alignment circuitry including a power of two generator and a selection network coupled to the compute circuitry, the mantissa product using a power-of-two value corresponding to the product exponent;
• accumulating partial results, by accumulation circuitry coupled to outputs of the compute circuitry, including a plurality of parallel adder trees and a hierarchical output accumulator;
• and
• normalizing accumulated results, by normalization circuitry coupled to the hierarchical output accumulator of the accumulation circuitry, configured to form an output value in a numeric format using a wider intermediate precision.

An apparatus for processing operand values in multiple numeric formats, including:

• a processing system configured to select a mode including at least a floating-point mode, to select a precision from multiple precisions, and to gate portions of the apparatus responsive to the selected mode and the selected precision;
• operand storage for operand values;
• compute circuitry configured, in the floating‑point mode, to produce a mantissa product and a product exponent;
• alignment circuitry including a power‑of‑two generator and a selection network coupled to the compute circuitry;
• accumulation circuitry coupled to the outputs of the compute circuitry, including a plurality of parallel adder trees and a hierarchical output accumulator;
• format preprocessing circuitry arranged along input paths and coupled between the operand storage and at least one of the compute circuitry and the accumulation circuitry, and configured to route element representations of different bit-widths through shared lanes;
• and
• normalization circuitry coupled to the hierarchical output accumulator of the accumulation circuitry, configured to form an output value in a numeric format using a wider intermediate precision.