System and methods of lithographic exposure to improve etch performance and yield

A method of processing a wafer, the method comprising:

• identifying a wafer and an exposure layout to be applied to the wafer using a first photolithography system, the exposure layout including exposure fields for lithographic exposure using a photomask, each exposure field including one or more die patterns, the wafer having a wafer perimeter defining a working surface for receiving lithographic exposure patterns;
• identifying, from the exposure layout, first die locations that are positioned fully within the wafer perimeter and second die locations that are not positioned fully within the wafer perimeter;
• receiving the wafer before or after the first photolithography system has executed a first photolithographic exposure that exposes the first die locations to a first pattern of actinic radiation resulting in a first latent pattern formed in a layer of photoresist deposited on the wafer within the first die locations, while the second die locations were not exposed by the first photolithography system;
• and
• executing a second photolithographic exposure that exposes at least a portion of the second die locations to a second pattern of actinic radiation using a second photolithography system resulting in a second latent pattern formed in the layer of photoresist within the at least portion of second die locations, the second pattern of actinic radiation having a different geometrical pattern compared to the first pattern of actinic radiation, while the second pattern of actinic radiation matches a pattern density of the first pattern of actinic radiation within a predetermined value of variation.

A coater-developer system for processing a semiconductor wafer, the coater-developer system comprising:

• an equipment front-end module having a mechanism for loading and unloading one or more wafers to be processed;
• a wafer processing region having multiple wafer processing modules including modules configured for coating wafers via spin-on deposition, modules configured for baking wafers, and modules configured for developing exposed wafers;
• a tool interface module defining a region to physically connect the coater-developer tool to a photolithographic exposure tool for exposure of circuit patterns using EUV lithography, the tool interface module configured to collect and store a queue of wafers for transfer to and reception from the photolithographic exposure tool;
• a robotic wafer transport system configured to move wafers from the equipment front-end module to wafer processing region, configured to move wafers among wafer processing modules in the wafer process region, and configured to move wafers from the wafer processing region to the tool interface module;
• and
• an edge die exposure module positioned within the tool interface module, the edge die exposure module including a DUV exposure system having optics and a pattern generation mechanism to expose edge die regions with a pattern of actinic radiation that has a pattern density matching a pattern density of an EUV pattern of radiation corresponding to die locations fully on a working surface of the wafer, the edge die regions including die locations that are partially on the working surface of the wafer and extend beyond a wafer perimeter.