Techniques For Detecting Bandgap And Supply Voltages During Power-On-Reset

An integrated circuit comprising a test power-on-reset detector circuit, wherein the test power-on-reset detector circuit comprises:

• a trip-out detector circuit that generates a trip-out signal indicative of a supply voltage increasing above a trip-out level;
• a trip-in detector circuit that generates a trip-in signal indicative of the supply voltage decreasing below a trip-in level that is less than the trip-out level;
• and
• a latch circuit that stores values of the trip-out signal and of the trip-in signal to generate a power-on-reset signal during a test of the integrated circuit.

A method for testing an integrated circuit during a power-on-reset of the integrated circuit, the method comprising:

• generating first power-on-reset values based on first supply voltages using functional power-on-reset detector circuits in the integrated circuit;
• resetting test register circuits in the integrated circuit in response to a first power-on-reset signal generated by a test power-on-reset detector circuit in the integrated circuit;
• configuring multiplexer circuits in the integrated circuit to output the first power-on-reset values as second power-on-reset signals based on first selection values stored in the test register circuits;
• and
• configuring the multiplexer circuits to output second power-on-reset values stored in the test register circuits as the second power-on-reset signals based on second selection values stored in the test register circuits.