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US 2026/0239995 A1Published application
Carrier structure
AssigneeSiliconware Precision Industries Co., Ltd.
InventorsCheng-Liang HSU, Wan-Rou CHEN, Hsin-Yin CHANG, Tsung-Li LIN, Hsiu-Jung LI, Chiu-Lien LI, Fu-Quan XU, Yi-Wen LIU, Chih-Chieh SUN
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Abstract
A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.
Claims9
A carrier structure, comprising:
- a package substrate defined with a chip-placement area for a single chip, wherein the chip-placement area has a plurality of corners, wherein at least two positioning areas are respectively formed at two of the corners of the chip-placement area;
- a first alignment portion with a first pattern and disposed on a corner of one of the at least two positioning areas;
- and
- a second alignment portion with a second pattern and disposed on a corner of another one of the at least two positioning areas, wherein the first pattern and the second pattern are different.
1 more element
Dependencies are inferred from the claim text.