Semiconductor package and method for fabricating the same

A semiconductor package comprising:

• a redistribution structure;
• a plurality of conductive posts on the redistribution structure;
• a semiconductor stack on the redistribution structure, the semiconductor stack comprising a plurality of semiconductor dies that are stacked, the semiconductor stack being disposed to be spaced apart in a vertical direction from the redistribution structure, and each of the plurality of conductive posts being connected to a corresponding semiconductor die among the plurality of semiconductor dies;
• a molding material covering the semiconductor stack and the plurality of conductive posts on the redistribution structure;
• a dielectric layer on the molding material, the dielectric layer comprising a first surface contacting the semiconductor stack and the molding material, and a second surface opposite the first surface;
• and
• a metal layer covering all of the second surface and comprising a marking pattern.

A semiconductor package comprising:

• a first redistribution structure;
• a plurality of first conductive posts on the first redistribution structure;
• a plurality of second conductive posts on the first redistribution structure;
• a first semiconductor stack on the first redistribution structure, the first semiconductor stack comprising a plurality of first semiconductor dies that are stacked, the first semiconductor stack being disposed to be vertically spaced apart from the first redistribution structure, each of the plurality of first conductive posts being connected to a corresponding first semiconductor die of the plurality of first semiconductor dies;
• a first molding material covering the first semiconductor stack, the plurality of first conductive posts, and the plurality of second conductive posts on the first redistribution structure;
• a second redistribution structure on the first molding material, the second redistribution structure comprising a first dielectric layer and a plurality of vias in the first dielectric layer, each of the plurality of second conductive posts being connected to a corresponding via of the plurality of vias;
• a plurality of third conductive posts on the second redistribution structure;
• a second semiconductor stack on the second redistribution structure, the second semiconductor stack comprising a plurality of second semiconductor dies that are stacked, the second semiconductor stack being disposed to be vertically spaced apart from the second redistribution structure, each of the plurality of third conductive posts being connected to a corresponding second semiconductor die of the plurality of second semiconductor dies;
• a second molding material covering the second semiconductor stack and the plurality of third conductive posts on the second redistribution structure;
• a second dielectric layer on the second molding material, the second dielectric layer comprising a first surface contacting the second semiconductor stack and the second molding material, and a second surface opposite the first surface;
• and
• a metal layer covering all of the second surface and comprising a marking pattern.