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US 2026/0239949 A1Published application
Mdip semiconductor device including backfilled vias
AssigneeSanDisk Technologies LLC
InventorsJayavel Pachamuthu, Rama Shukla
Life of this patent
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Abstract
A mirrored die pair (mDiP) semiconductor device includes deep trench vias having portions at the upper and/or lower surfaces of the mDiP device that are backfilled with conductive material. Backfilling the deep trench vias ensures electrically coupled, solid, low resistive bonding, for example between a stack of mDiP semiconductor devices.
Claims20
A semiconductor device, comprising:
- a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising:
- a memory die,
- a first major planar surface,
- a second major planar surface,
- a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface;
- and
- conductive backfill material backfilling the concave meniscus in said each via, the backfill material bringing each said via flush with the first major planar surface.
4 more elements
A mirrored die pair (mDiP) semiconductor device, comprising:
- a first group of semiconductor dies, the first group of semiconductor dies comprising:
- a first memory die,
- a first CMOS logic circuit die bonded to the first memory die,
- a first major planar surface,
- a second major planar surface opposite the first major planar surface,
- a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface;
- and
- conductive backfill material backfilling the concave meniscus in said each via of the first set of vias, the backfill material bringing each said via of the first set of vias flush with the first major planar surface;
- and
- a second group of semiconductor dies bonded to the first group of semiconductor dies, the second group of semiconductor dies comprising:
- a second memory die,
- a second CMOS logic circuit die bonded to the second memory die,
- a third major planar surface, and
- a fourth major planar surface opposite the third major planar surface.
11 more elements
A semiconductor device, comprising:
- a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising:
- a memory die,
- a first major planar surface,
- a second major planar surface,
- a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface;
- and
- conductive backfill means for backfilling the concave meniscus in said each via and for bringing each said via flush with the first major planar surface.
4 more elements
Dependencies are inferred from the claim text.