RRAM Memory Cell Structure

A method of forming a resistive random access memory (RRAM) memory cell structure, comprising:

• forming a transistor on a semiconductor substrate that includes a source region, a drain region and a gate;
• forming a lower electrode disposed over the semiconductor substrate and electrically connected to the drain region;
• forming a source line electrically connected to the source region;
• forming a word line electrically connected to the gate;
• forming a first block of resistive switching dielectric material electrically connected to the lower electrode;
• forming a second block of resistive switching dielectric material electrically connected to the lower electrode;
• forming a first upper electrode electrically connected to the first block of resistive switching dielectric material;
• forming a second upper electrode electrically connected to the second block of resistive switching dielectric material;
• forming a first bit line electrically connected to the first upper electrode;
• and
• forming a second bit line electrically connected to the second upper electrode;
• wherein the first bit line and the second bit line are electrically isolated from each other except for the first and second blocks of resistive switching dielectric material.