Semiconductor device, display apparatus, and electronic device

A semiconductor device comprising:

• a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor,
• wherein a first gate of the first transistor is electrically connected to a first gate of the second transistor,
• wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, a first gate of the fourth transistor, a first gate of the seventh transistor, and one of a pair of electrodes of the first capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the fourth transistor and one of a source and a drain of the fifth transistor,
• wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a pair of electrodes of the second capacitor and a gate of the sixth transistor,
• wherein one of a source and a drain of the sixth transistor is electrically connected to the other of the pair of electrodes of the second capacitor and one of a source and a drain of the seventh transistor,
• wherein the second transistor and the fourth transistor each comprise a first conductive layer configured to be the one of the source and the drain, a second conductive layer configured to be the other of the source and the drain, a third conductive layer configured to be the first gate, a semiconductor layer, and a gate insulating film,
• wherein the first conductive layer and the second conductive layer each comprise a region in contact with a top surface of a first insulating layer,
• wherein the semiconductor layer comprises a region in contact with a side surface of an opening formed in the first insulating layer, a top surface of a second insulating layer in a bottom portion of the opening, a top surface of the first conductive layer, and a top surface of the second conductive layer,
• wherein the gate insulating film comprises a region in contact with a top surface of the semiconductor layer, the top surface of the first conductive layer, and the top surface of the second conductive layer,
• wherein the third conductive layer comprises a region overlapping with at least part of the semiconductor layer and in contact with a top surface of the gate insulating film, and
• wherein the second transistor and the fourth transistor each comprise a channel formation region in the semiconductor layer.