US 2026/0239740 A1 · SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

Abstract

A fin-based transistor includes a gate structure that is vertically-arranged with source/drain structures of the fin-based transistor. The gate structure may wrap around the top and sides of a fin structure of the fin-based transistor, and source/drain structures of the fin-based transistor are located on a bottom of the fin structure. Source/drain contacts of the fin-based transistor are located on the source/drain structures over the bottom of the fin structure. This enables the gate structure and the source/drain contacts to be located on vertically opposing sides of the fin structure, thereby enabling gate spacers to be omitted from the fin-based transistor.

Claims20

Dependent claims

A semiconductor device, comprising:

a semiconductor protruding structure on a first side of the semiconductor device;
a gate structure on the first side of the semiconductor device, the gate structure adjacent to the semiconductor protruding structure and on a first side of the semiconductor protruding structure;
and
a source or drain structure on a second side of the semiconductor device, opposing the first side, the source or drain structure adjacent to a second side of the semiconductor protruding structure.

1 more element

A method, comprising:

forming a fin structure on a substrate, the fin structure including a sacrificial portion on the substrate and a semiconductor portion on the sacrificial portion;
forming a gate structure adjacent to the fin structure;
removing the substrate, which exposes the sacrificial portion of the fin structure;
removing a first part of the sacrificial portion that overlaps the gate structure, wherein a second part of the sacrificial portion remains on the semiconductor portion;
recessing the semiconductor portion to form a recessed portion, the recessing using the second part of the sacrificial portion as a mask;
forming a dielectric layer in the recessed portion;
removing the second part of the sacrificial portion to expose the semiconductor portion;
and
forming a source or drain structure on the exposed semiconductor portion.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/231,251Filed 6 Jun 2025

Priority

12 Feb 2025

Published

13 Aug 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 86/215
The substrates comprising an insulating layer on a semiconductor body, e.g. SOI: comprising FinFETs
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 62/121
Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates

Semiconductor device and methods of formation

Life of this patent

Semiconductor device and methods of formation

Life of this patent

Abstract

Claims20