Method for manufacturing semiconductor device
AssigneeShanghai Huali Integrated Circuit Corporation
InventorsQiwei WANG, Shiyou PAN, Wei ZHAO
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Abstract
The present disclosure provides a method for manufacturing an embedded high-voltage HKMG semiconductor device. A hard mask layer is first formed before forming a well region of a first-conductivity-type doped device and a well region of a second-conductivity-type doped device, an opening in the hard mask layer is formed in the steps of forming the well region of the first-conductivity-type doped device and the well region of the second-conductivity-type doped device, and then the hard mask layer serves as a barrier layer to etch the medium-voltage device region, eliminating the need for defining an active area recess etching in the medium-voltage device region, thereby reducing the number of photomasks and lowering costs.
Claims10
A method for manufacturing a semiconductor device, comprising:
- S1:
- providing a semiconductor substrate, forming a sacrificial layer on an upper surface of the semiconductor substrate, wherein the semiconductor substrate is divided into a first voltage device region, a second voltage device region, and a third voltage device region, wherein the second voltage device region comprises a first-conductivity-type doped device region and a second-conductivity-type doped device region;
- S2:
- forming a hard mask layer on the sacrificial layer, forming a first photoresist layer on the hard mask layer, patterning the first photoresist layer using a first photomask to form a first opening, wherein the first opening exposes the hard mask layer above the first-conductivity-type doped device region;
- S3:
- etching the hard mask layer aligned to the patterned first photoresist layer to form a second opening, and performing ion implantation on the first-conductivity-type doped device region into the second opening to form a well region of the first-conductivity-type doped device region;
- S4:
- forming a second photoresist layer on the hard mask layer and the seond opening in the hard mask layer, patterning the second photoresist layer using a second photomask to form a third opening, wherein the third opening exposes the hard mask layer above the second-conductivity-type doped device region;
- S5:
- etching the hard mask layer aligned to the third hole in the patterned second photoresist layer to form a fourth opening in the hard mask layer, and performing ion implantation on the second-conductivity-type doped device region aligned to the third and the fourth openings to form a well region of the second-conductivity-type doped device region;
- S6:
- etching to remove the secondphotoresist layer and the sacrificial layer above the second voltage device region using the second and fourth openings as a mask, and further etching the second voltage device region to a predetermined depth to form a trench in the second voltage device region;
- and
- S7:
- forming a first gate dielectric layer for the second voltage device region in the trench of the second voltage device region.
Dependencies are inferred from the claim text.