Semiconductor devices with field relief layers and integrated methods of fabrication thereof

A method of fabricating a semiconductor device, comprising:

• forming a first transistor including:
• (i) a first field relief layer on a first surface of a semiconductor layer, the first field relief layer being a step-oxide field relief layer formed from a first local oxidation of silicon (LOCOS) layer, (ii) a first drain region, (iii) a first source region, and (iv) a first gate stack, the first drain region being proximate to a first end of the first field relief layer, the first source region being proximate to a second end of the first field relief layer, and the first gate stack being between the first drain region and the first source region and partially over the first field relief layer;
• and
• forming a second transistor including:
• (i) a second field relief layer on a second surface of the semiconductor layer, the second field relief layer being a second LOCOS field relief layer formed via the same LOCOS process as the first LOCOS layer, (ii) a second drain region, (iii) a second source region, and (iv) a second gate stack, the second drain region being proximate to a first end of the second field relief layer, the second source region being proximate to a second end of the second field relief layer, and the second gate stack being between the second drain region and the second source region and partially over the second field relief layer.

A semiconductor device, comprising:

• a semiconductor layer;
• a first transistor disposed in a first region of the semiconductor layer, the first transistor including:
• a first field relief layer;
• a first drain region disposed proximate to a first end of the first field relief layer;
• a first source region disposed proximate to a second end of the first field relief layer;
• and
• a first gate stack including a first gate electrode and a first gate dielectric layer, the first gate stack disposed between the first drain region and the first source region and partially over the first field relief layer;
• and
• a second transistor disposed in a second region of the semiconductor layer different than the first region, the second transistor including a second gate dielectric layer, the first gate dielectric layer being recessed relative to the second gate dielectric layer.