Semiconductor device

A semiconductor device comprising:

• a substrate comprising a first surface and a second surface opposite to the first surface;
• a first active pattern on the first surface of the substrate and extending in a first direction;
• a second active pattern on the first surface of the substrate and spaced apart from the first active pattern in a second direction intersecting the first direction, wherein the second active pattern extends in the first direction;
• a first gate structure on the first active pattern and extending in the second direction;
• a second gate structure on the second active pattern and extending in the second direction;
• a first epitaxial pattern on at least one side of the first gate structure and connected to the first active pattern;
• a second epitaxial pattern on at least one side of the second gate structure and connected to the second active pattern;
• a frontside source/drain contact on an upper surface of the second epitaxial pattern and connected to the second epitaxial pattern;
• a frontside wiring structure on an upper surface of the frontside source/drain contact and connected to the frontside source/drain contact;
• a backside contact via in the substrate and extending in the second direction;
• a first backside source/drain contact on a lower surface of the first epitaxial pattern and connecting the backside contact via to the first epitaxial pattern;
• a second backside source/drain contact on a lower surface of the second epitaxial pattern and connecting the backside contact via to the second epitaxial pattern;
• a first backside wiring pattern on the second surface of the substrate and connected to the backside contact via;
• and
• a second backside wiring pattern on the second surface of the substrate and spaced apart from the first backside wiring pattern in the second direction, wherein the second backside wiring pattern is connected to the backside contact via.

A semiconductor device comprising:

• a substrate comprising a first surface and a second surface opposite to the first surface;
• a first active pattern on the first surface of the substrate and extending in a first direction;
• a first gate structure on the first active pattern and extending in a second direction intersecting the first direction;
• a first epitaxial pattern on each of opposing sides of the first gate structure and connected to the first active pattern;
• a first frontside source/drain contact on an upper surface of the first epitaxial pattern and connected to the first epitaxial pattern;
• a frontside wiring structure on an upper surface of the first frontside source/drain contact and connected to the first frontside source/drain contact;
• an insulating pattern on a lower surface of the first gate structure and extending in the second direction to partition the substrate;
• a first backside contact via on a first side of the insulating pattern;
• a second backside contact via on a second side of the insulating pattern;
• a first backside source/drain contact connecting the first backside contact via to the first epitaxial pattern;
• a second backside source/drain contact connecting the second backside contact via to the first epitaxial pattern;
• a first backside wiring pattern on the second surface of the substrate and connected to the first backside contact via;
• and
• a second backside wiring pattern on the second surface of the substrate and spaced apart from the first backside wiring pattern in the first direction, wherein the second backside wiring pattern is connected to the second backside contact via.