Memory device and fabrication method thereof

A method of fabricating a memory device, comprising:

• forming a shallow trench isolation (STI) region in a substrate to divide the substrate into a first substrate region and a second substrate region;
• forming an epitaxy layer on the first substrate region, wherein the second substrate region is exposed;
• forming a high-k dielectric layer on the epitaxy layer and the second substrate region;
• forming a first sacrificial layer on a first portion of the high-k dielectric layer above the first substrate region, wherein a second portion of the high-k dielectric layer above the second substrate region is exposed;
• forming a metal layer on the first sacrificial layer and the high-k dielectric layer;
• performing an annealing process to form a doping region in the high-k dielectric layer above the second substrate region;
• removing the metal layer and the first sacrificial layer;
• forming a gate electrode layer on the high-k dielectric layer and a gate capping layer on the gate electrode layer;
• and
• patterning the gate capping layer, the gate electrode layer, and the high-k dielectric layer into a first gate structure above the epitaxy layer and a second gate structure above the doping region.