Three-dimensional semiconductor devices

A three-dimensional (3D) semiconductor device comprising:

• a lower channel pattern;
• a pair of lower source/drain patterns on opposing side surfaces of the lower channel pattern, respectively;
• an upper channel pattern on the lower channel pattern;
• a pair of upper source/drain patterns on opposing side surfaces of the upper channel pattern, respectively;
• a dummy channel pattern between the lower channel pattern and the upper channel pattern;
• a pair of liner layers on opposing side surfaces of the dummy channel pattern, respectively;
• and
• a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern,
• wherein the gate electrode comprises a lower gate electrode on the lower channel pattern and an upper gate electrode on the upper channel pattern, and
• wherein each of the liner layers horizontally overlaps with the lower gate electrode and the upper gate electrode.

A three-dimensional (3D) semiconductor device comprising:

• a first active region on a substrate, the first active region comprising a lower channel pattern and a lower source/drain pattern electrically connected to the lower channel pattern;
• a second active region on the first active region, the second active region comprising an upper channel pattern and an upper source/drain pattern electrically connected to the upper channel pattern;
• a dummy channel pattern between the lower channel pattern and the upper channel pattern;
• a gate electrode on the lower channel pattern, the dummy channel pattern, and the upper channel pattern;
• and
• a liner layer on a side surface of the dummy channel pattern, the liner layer horizontally overlapping with the gate electrode,
• wherein the gate electrode comprises a first portion between the lower channel pattern and the dummy channel pattern and a second portion between the dummy channel pattern and the upper channel pattern,
• the first portion comprises a first metal nitride layer and a metal carbide layer,
• the second portion comprises a second metal nitride layer, and
• a thickness of the second metal nitride layer in a vertical direction is different from a thickness of the first metal nitride layer in the vertical direction.

A three-dimensional (3D) semiconductor device comprising:

• a lower channel pattern on a substrate, the lower channel pattern comprising a first semiconductor pattern and a second semiconductor pattern that is spaced apart from the first semiconductor pattern;
• an upper channel pattern on the lower channel pattern, the upper channel pattern comprising a third semiconductor pattern and a fourth semiconductor pattern that is spaced apart from the third semiconductor pattern;
• a dummy channel pattern between the second semiconductor pattern and the third semiconductor pattern;
• a gate electrode in which the first, second, third and fourth semiconductor patterns and the dummy channel pattern are provided;
• and
• a liner layer on a side surface of the dummy channel pattern,
• wherein the liner layer horizontally overlaps with the gate electrode,
• the first, second, third and fourth semiconductor patterns and the dummy channel pattern are vertically overlapped with each other, and
• a thickness of the dummy channel pattern in a vertical direction is thicker than respective thicknesses of the first, second, third and fourth semiconductor patterns in the vertical direction.