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US 2026/0239693 A1Published application
Source/drain features for stacked multi-gate device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorWinnie Victoria Wei-Ning Chen
Life of this patent
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Abstract
Semiconductor structures and processes of forming the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a first source/drain feature disposed on the substrate, a first contact etch stop layer disposed on the first source/drain feature, a first dielectric layer disposed over the first CESL, an etch stop layer (ESL) disposed on and in contact with the first CESL and the first dielectric layer, a second source/drain feature disposed over the ESL, a second (CESL) disposed on the second source/drain feature, a second dielectric layer disposed over the second CESL. The first source/drain feature includes silicon and an n-type dopant and the second source/drain feature includes silicon germanium and a p-type dopant.
Claims20
A method, comprising:
- forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the stack and a portion of the substrate to form a first fin-shaped structure and a second fin-shaped structure, the first fin-shaped structure comprising a first base portion formed from the substrate and a first stack portion formed from the stack, the second fin-shaped structure comprising a second base portion formed from the substrate and a second stack portion formed from the stack;
- forming an isolation feature over the substrate to interface sidewalls of the first base portion and the second base portion;
- forming a dummy gate stack over channel regions of the first fin-shaped structure and the second fin-shaped structure;
- recessing source/drain regions of the first fin-shaped structure and the second fin-shaped structure to form a first source/drain recess over the first fin-shaped structure and a second source/drain recess over the second fin-shaped structure;
- forming a first mask layer over the second source/drain recess;
- with the first mask layer covering the second source/drain recess, depositing a first source/drain feature over the first source/drain recess;
- removing the first mask layer;
- forming a second mask layer over the first source/drain feature;
- with the first source/drain feature covered by the second mask layer, depositing a second source/drain feature over the second source/drain recess;
- performing an anneal process in presence of an oxygen source to form a surface oxide layer over the second source/drain feature;
- selectively removing the surface oxide layer to form a modified second source/drain feature;
- after the selectively removing, removing the second mask layer;
- forming a contact etch stop layer (CESL) over the first source/drain feature and the modified second source/drain feature;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers over the channel regions to form first channel members over the first base portion and second channel members over the second base portion;
- and
- forming a first gate structure to wrap around the first channel members and a second gate structure to wrap around the second channel members,
- wherein a composition of the first source/drain feature is different from a composition of the second source/drain feature.
16 more elements
A method, comprising:
- forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the stack and a portion of the substrate to form a first fin-shaped structure and a second fin-shaped structure, the first fin-shaped structure comprising a first base portion formed from the substrate and a first stack portion formed from the stack, the second fin-shaped structure comprising a second base portion formed from the substrate and a second stack portion formed from the stack;
- forming an isolation feature over the substrate to interface sidewalls of the first base portion and the second base portion;
- forming a dummy gate stack over channel regions of the first fin-shaped structure and the second fin-shaped structure;
- recessing source/drain regions of the first fin-shaped structure and the second fin-shaped structure to form a first source/drain recess over the first fin-shaped structure and a second source/drain recess over the second fin-shaped structure;
- forming a first mask layer over the second source/drain recess;
- with the first mask layer covering the second source/drain recess, depositing a first source/drain feature over the first source/drain recess;
- removing the first mask layer;
- forming a second mask layer over the first source/drain feature;
- with the first source/drain feature covered by the second mask layer, depositing a second source/drain feature over the second source/drain recess;
- performing an anneal process in presence of an oxygen source to form a surface oxide layer over the second source/drain feature;
- selectively removing the surface oxide layer to form a modified second source/drain feature;
- after the selectively removing, removing the second mask layer;
- forming a contact etch stop layer (CESL) over the first source/drain feature and the modified second source/drain feature;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers over the channel regions to form first channel members over the first base portion and second channel members over the second base portion;
- and
- forming a first gate structure to wrap around the first channel members and a second gate structure to wrap around the second channel members,
- wherein the first source/drain feature comprises silicon and an n-type dopant,
- wherein the second source/drain feature comprises silicon germanium and a p-type dopant.
17 more elements
A method, comprising:
- forming a stack over a substrate, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
- patterning the stack and a portion of the substrate to form a first fin-shaped structure and a second fin-shaped structure, the first fin-shaped structure comprising a first base portion formed from the substrate and a first stack portion formed from the stack, the second fin-shaped structure comprising a second base portion formed from the substrate and a second stack portion formed from the stack;
- forming an isolation feature over the substrate to interface sidewalls of the first base portion and the second base portion;
- forming a dummy gate stack over channel regions of the first fin-shaped structure and the second fin-shaped structure;
- recessing source/drain regions of the first fin-shaped structure and the second fin-shaped structure to form a first source/drain recess over the first fin-shaped structure and a second source/drain recess over the second fin-shaped structure;
- forming a first mask layer over the second source/drain recess;
- with the first mask layer covering the second source/drain recess, depositing a first source/drain feature over the first source/drain recess;
- removing the first mask layer;
- forming a second mask layer over the first source/drain feature;
- with the first source/drain feature covered by the second mask layer, depositing a second source/drain feature over the second source/drain recess;
- performing an anneal process in presence of an oxygen source to form a surface oxide layer over the second source/drain feature;
- selectively removing the surface oxide layer to form a modified second source/drain feature;
- after the selectively removing, removing the second mask layer;
- forming a contact etch stop layer (CESL) over the first source/drain feature and the modified second source/drain feature;
- removing the dummy gate stack;
- selectively removing the plurality of sacrificial layers over the channel regions to form first channel members over the first base portion and second channel members over the second base portion;
- and
- forming a first gate structure to wrap around the first channel members and a second gate structure to wrap around the second channel members,
- wherein the first source/drain feature comprises silicon and an n-type dopant,
- wherein the second source/drain feature comprises silicon germanium and a p-type dopant,
- wherein, after the forming of the second source/drain feature, a thickness of the second source/drain feature is greater than a thickness of the first source/drain feature.
18 more elements
Dependencies are inferred from the claim text.