US 2026/0239688 A1Published application

Electronic device manufacturing method

AssigneeSTMicroelectronics (Crolles 2) SAS

InventorsRemy BERTHELON, Olivier WEBER

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Abstract

The present description concerns a method of manufacturing a device comprising a first portion having an array of memory cells formed therein and a second portion having transistors formed therein, the method comprising: a. the forming of first insulating trenches separating from one another the substrate regions of a same cell row, and b. the forming of second trenches separating from one another the regions of a same cell column, the second trenches having a height greater than the height of the first trenches, step a. comprising the independent forming of a lower portion and of an upper portion of each first trench, the forming of the upper portions comprising the deposition of a first insulating layer, the etching of the portions of the first insulating layer which are not located on the upper portions.

Claims20

Dependent claims

A device, comprising:

a substrate having a first surface opposite a second surface;
a first plurality of trenches in the substrate extending along a first direction transverse to the first surface of the substrate, each of the first plurality of trenches including:
a first portion including a first insulating material, the first portion having a first surface that is coplanar with the first surface of the substrate and extending a first distance into the substrate along the first direction;
a second portion having a first surface coupled to the first surface of each first portion and extending away from the substrate along the first direction, the first surface of each second portion being opposite a second surface of each second portion;
and
a first metal layer coupled to the second surface of each second portion;
a second plurality of trenches in the substrate extending along the first direction transverse to the first surface of the substrate, each of the second plurality of trenches having a first surface in the substrate and a second surface opposite the first surface extending out of the substrate, each of the second plurality of trenches including a second insulating material;
and
a second metal layer coupled to the second surface of each of the second plurality of trenches.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/639,647Filed 6 Apr 2026
Priority: FR FR220585316 Jun 2022
Published: 13 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10B 63/30
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: comprising selection components having three or more electrodes, e.g.…
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10B 63/80
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon

Family

Application18/330,287Division · filed 6 Jun 2023
Application19/639,647Division
US 12,641,841 B2Related patent
US 2023/0411450 A1Published application
US 2026/0239688 A1This patent

From the US filing history. Foreign family members aren’t listed.