US 2026/0239679 A1Published application

Semiconductor structure and fabrication method thereof

AssigneeNanya Technology Corporation

InventorYing-Cheng Chuang

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Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate with active areas, shallow trench isolation (STI) structures disposed in the substrate, word lines embedded in the substrate, a first barrier layer, work function control structures, and a cap layer. Each word line includes active portions overlapping with corresponding ones of the active areas and passing portions overlapping with corresponding ones of the STI structures. The first barrier layer is disposed on top surfaces of the active portions and top surfaces of the passing portions. The work function control structures are disposed over the first barrier layer and the top surfaces of the active portions. The cap layer includes first portions and second portions. The first portions are located above the active portions. The second portions are located above the passing portions.

Claims10

Dependent claims

A semiconductor structure, comprising:

a substrate with a plurality of active areas;
a plurality of shallow trench isolation structures, disposed in the substrate;
a plurality of word lines, embedded in the substrate, wherein each word line comprises a plurality of active portions overlapping with corresponding ones of the plurality of active areas and a plurality of passing portions overlapping with corresponding ones of the plurality of shallow trench isolation structures;
a first barrier layer, disposed on top surfaces of the plurality of active portions and top surfaces of the plurality of passing portions;
a plurality of work function control structures, disposed over the first barrier layer and the top surfaces of the active portions;
and
a cap layer, comprising:
a plurality of first portions, located above the plurality of active portions;
and
a plurality of second portions, located above the plurality of passing portions, wherein a length of the plurality of second portions extending into the substrate is longer than a length of the plurality of first portions extending into the substrate.

7 more elements

A fabrication method of a semiconductor structure, comprising:

providing a substrate with a plurality of active areas and a plurality of shallow trench isolation structures embedded in the substrate;
forming a plurality of word lines in the substrate, wherein each word line comprises a plurality of active portions overlapping with corresponding ones of the plurality of active areas and a plurality of passing portions overlapping with corresponding ones of the plurality of shallow trench isolation structures;
forming a first barrier layer on top surfaces of the plurality of active portions and top surfaces of the plurality of passing portions;
forming a work function control material layer above the plurality of word lines;
removing a portion of the work function control material layer over the plurality of passing portions, wherein remaining portions of the work function control material layer form a plurality of work function control structures over the plurality of active portions;
and
forming a cap layer above the plurality of active portions and the plurality of passing portions.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/048,835Filed 7 Feb 2025
Published: 13 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 62/102
Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies: constructional design…
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate
H10B 12/34
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the transistor being at least partially in a trench in the substrate