3d semiconductor device and structure with metal layers and a power delivery path

A semiconductor device, the device comprising:

• a first level comprising a plurality of transistors,
• wherein said plurality of transistors comprise a first single crystal silicon;
• a first metal layer disposed over said first level;
• a second metal layer disposed over said first metal layer;
• an isolation layer disposed over said second metal layer;
• a first silicon layer comprising second single crystal silicon,
• wherein said first silicon layer is disposed over said isolation layer, and
• wherein said isolation layer comprises an oxide to oxide bonding surface;
• a plurality of capacitors;
• and
• a third metal layer disposed under said first level,
• wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said first metal layer,
• wherein said first level comprises a first transistor channel and a second transistor channel, and
• wherein said second transistor channel overlays said first transistor channel.

A semiconductor device, the device comprising:

• a first level comprising a plurality of transistors,
• wherein said plurality of transistors comprise first single crystal silicon;
• a first metal layer disposed over said first level;
• a second metal layer disposed over said first metal layer;
• an isolation layer disposed over said second metal layer;
• a first silicon layer comprising second single crystal silicon disposed over said isolation layer,
• wherein said isolation layer comprises an oxide to oxide bonding surface;
• a plurality of vias disposed through said first level;
• and
• a third metal layer disposed under said first level,
• wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said first metal layer,
• wherein said first level comprises a first transistor channel and a second transistor channel, and
• wherein said second transistor channel and said first transistor channel are controlled by the same gate line.