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US 2026/0239654 A1Published application
Method and system for vertical gan jfet with isolated back barrier
AssigneeAlithia Power Inc.
InventorsCristofer Ugolini, Allen Hanson
Life of this patent
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Abstract
Techniques are disclosed for a vertical GaN junction field effect transistor (JFET). The JFET can include a substrate, a drift layer coupled to the substrate, a channel layer coupled to the drift layer at the interface, a gate layer coupled to the channel layer, and source, gate, and drain contacts. The JFET can also include a barrier region formed within the drift layer at a location below the interface of the drift layer. The barrier region can define a lateral channel of the JFET extending between the barrier region and the gate.
Claims20
A field effect transistor comprising:
- a substrate;
- a drift layer coupled to the substrate, wherein the drift layer comprises an interface and a barrier region disposed within the drift layer at a location between the interface and the substrate;
- a channel layer coupled to the drift layer at the interface;
- a gate layer coupled to the channel layer;
- a source contact electrically connected to the channel layer;
- a gate contact electrically connected to the gate layer;
- and
- a drain contact electrically connected to the substrate.
5 more elements
A method comprising:
- providing a substrate;
- forming a gallium nitride (GaN) drift layer on the substrate, the GaN drift layer comprising a surface opposite an interface with the substrate;
- forming a barrier region within the GaN drift layer at a location between the surface and the substrate;
- forming a channel layer on the surface of the GaN drift layer;
- forming a gate layer on the channel layer;
- patterning the gate layer to form a plurality of gates separated by a channel;
- and
- forming gate contacts on the plurality of gates, a source contact on the channel, and a drain contact on the substrate.
5 more elements
Dependencies are inferred from the claim text.