HIGH STABILITY GaN DEVICE AND GaN BRIDGE INTEGRATED CIRCUIT
AssigneePeking University
InventorsJin WEI, Junjie Yang
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Abstract
The present disclosure discloses a high stability GaN device and a GaN bridge integrated circuit. The GaN device include: a substrate; and a transition layer, a buffer layer, a hole blocking layer, a channel layer, and a barrier layer sequentially stacked on the substrate; a source and a drain of the GaN device disposed in an active region above the barrier layer; a gate of the GaN device located between the source and the drain; and a hole injection layer formed between the gate and the barrier layer, wherein the hole blocking layer is inserted between the channel layer and the buffer layer and the top of a valence band of the hole barrier layer is lower than the top of a valence band of the channel layer.
Claims10
A GaN device, comprising:
- a substrate;
- and
- a transition layer, a buffer layer, a hole blocking layer, a channel layer, and a barrier layer sequentially stacked on the substrate;
- a source and a drain of the GaN device disposed in an active region above the barrier layer;
- a gate of the GaN device located between the source and the drain;
- and
- a hole injection layer formed between the gate and the barrier layer,
- wherein the hole blocking layer is inserted between the channel layer and the buffer layer and the top of a valence band of the hole barrier layer is lower than the top of a valence band of the channel layer.
A GaN bridge integrated circuit, comprising:
- two GaN transistors that share a common substrate, one of which serves as an upper transistor and the other serves as a low-side transistor, wherein a source of the upper transistor is connected to a drain of the lower transistor,
- wherein the substrate is configured by one of the followings:
- being floating,
- including an ohmic contact located on the back of the substrate and connected to a source of the low-side transistor, or
- including an ohmic contact located on the back of the substrate and connected to the source of the upper transistor, and
- wherein each of the upper transistor and the low-side transistor comprises:
- a transition layer, a buffer layer, a hole blocking layer, a channel layer, and a barrier layer sequentially stacked on the substrate;
- a source and a drain of the GaN transistor disposed in an active region above the barrier layer;
- a gate of the GaN transistor located between the source and the drain;
- and
- a hole injection layer formed between the gate and the barrier layer,
- wherein the hole blocking layer is inserted between the channel layer and the buffer layer and the top of a valence band of the hole barrier layer is lower than the top of a valence band of the channel layer.
Dependencies are inferred from the claim text.