Methods of tuning gate dielectrics and the structures thereof

A method comprising:

• forming a plurality of semiconductor nanostructures and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are located alternatingly;
• removing the plurality of sacrificial layers to leave spaces between the plurality of semiconductor nanostructures;
• oxidizing outer portions of the plurality of semiconductor nanostructures to form oxide layers that encircle inner portions of the plurality of semiconductor nanostructures, wherein each of the oxide layers comprises:
• sidewall portions on sidewalls of the inner portions of the plurality of semiconductor nanostructures, wherein the sidewall portions have a first thickness;
• and
• top portions on tops of the inner portions of the plurality of semiconductor nanostructures, wherein the top portions have a second thickness smaller than the first thickness;
• and
• forming a gate stack in the spaces between the plurality of semiconductor nanostructures.

A method comprising:

• forming a plurality of semiconductor nanostructures, wherein upper ones of the plurality of semiconductor nanostructures overlap lower ones of the plurality of semiconductor nanostructures;
• forming source and drain regions joining to opposing ends of the plurality of semiconductor nanostructures;
• forming an oxide layer encircling a nanostructure of the plurality of semiconductor nanostructures, wherein the oxide layer comprises:
• a sidewall portion on a sidewall of the nanostructure, wherein the sidewall portion has a first thickness;
• and
• a top portion overlying the nanostructure;
• and
• a bottom portion overlying the nanostructure, wherein the top portion and the bottom portion have second thicknesses smaller than the first thickness;
• and
• forming a gate stack, wherein the gate stack comprises parts in spacings between the plurality of semiconductor nanostructures.