Super-junction igbt device with separation gate structures and preparation method thereof

A preparation method of a super-junction IGBT device with separation gate structures, comprising steps:

• S100:
• providing an N-type doped silicon substrate;
• S200:
• epitaxially growing N-type doped silicon on the N-type doped silicon substrate to form an epitaxial layer, and forming P-pillars disposed along a first direction by performing ion implantation on the epitaxial layer, wherein portions of the epitaxial layer disposed between the P-pillars are defined as N-pillars;
• S300:
• performing the ion implantation on an upper portion of the epitaxial layer to form a P-base region, and forming two trenches above each of the N-pillars;
• wherein the two trenches extend downward to penetrate through the P-base region and extend into each of the N-pillars;
• S400:
• forming N+regions and P+regions periodically disposed in a second direction at an upper end of the P-base region and between the two trenches disposed above each of the N-pillars by performing the ion implantation, and forming a N-base region and a first P+layer at the upper end of the P-base region and between each two adjacent N-pillars by performing the ion implantation;
• S500:
• forming separation gates respectively in the trenches;
• S600:
• forming an emitter metal at an upper end of the epitaxial layer, forming a second P+layer by performing the ion implantation on the N-type doped silicon substrate, and forming a back metal at a lower end of the second P+layer.