Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsKouhei TOYOTAKA, Yuto YAKUBO
Life of this patent
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Abstract
A semiconductor device with high reliability is provided. A latch circuit including Si transistors is combined with a memory circuit including OS transistors. A soft error is less likely to occur in the memory circuit including OS transistors. The logic value of the latch circuit and the logic value of the memory circuit including OS transistors are compared and a comparison result is output. The logic value of the latch circuit is inverted in accordance with the comparison result. High-speed operation by the latch circuit including Si transistors and high reliability by the memory circuit including OS transistors are achieved.
Claims9
A semiconductor device comprising:
- a first memory circuit and a second memory circuit,
- wherein the semiconductor device:
- is configured to compare a logic value of first data retained in the first memory circuit with a logic value of second data retained in the second memory circuit,
- wherein the semiconductor device is configured to output first signal corresponding to a comparison result,
- wherein the first memory circuit comprises a transistor comprising silicon in a channel formation region, and
- wherein the second memory circuit comprises a transistor comprising an oxide semiconductor in a channel formation region.
A semiconductor device comprising:
- a first memory circuit and a second memory circuit,
- wherein the first memory circuit comprises a first inverter circuit, a second inverter circuit, a first transistor, and a second transistor,
- wherein an output of the first inverter circuit is electrically connected to an input of the second inverter circuit,
- wherein an output of the second inverter circuit is electrically connected to an input of the first inverter circuit,
- wherein the output of the first inverter circuit is electrically connected to a first wiring through a source and a drain of the first transistor,
- wherein the output of the second inverter circuit is electrically connected to a second wiring through a source and a drain of the second transistor,
- wherein the second memory circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor and a capacitor,
- wherein one of a source and a drain of the third transistor is electrically connected to the output of the first inverter circuit and one of a source and a drain of the fourth transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to one terminal of the capacitor and a gate of the fourth transistor,
- wherein one of a source and a drain of the fifth transistor is electrically connected to the output of the second inverter circuit and one of a source and a drain of the sixth transistor,
- wherein the other of the source and the drain of the fifth transistor is electrically connected to the other terminal of the capacitor and a gate of the sixth transistor,
- wherein a gate of the third transistor is electrically connected to a gate of the fifth transistor,
- wherein the other of the source and the drain of the fourth transistor and the other of the source and the drain of the sixth transistor are electrically connected to one of a source and a drain of the seventh transistor, and
- wherein the other of the source and the drain of the seventh transistor is electrically connected to a third wiring.
Dependencies are inferred from the claim text.